1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having a wiring evaluation circuit for evaluating wiring formed on a chip when a semiconductor fabrication process or the like is developed, and to an evaluation method of the wiring in the semiconductor integrated circuit.
2. Description of the Related Art
When a new semiconductor fabrication process is developed, an evaluation chip is generally used to evaluate the shape of wiring fabricated by this process, the characteristics of elements, and so on. On the evaluation chip, a wiring evaluation circuit, an element evaluation circuit, and so on are formed. In the wiring evaluation circuit, a plurality of kinds of evaluation wirings with different wiring widths and wiring intervals are formed. Then, failure (break, short, and so on) occurring in each of the evaluation wirings is evaluated, thereby determining optimum fabrication process conditions and process margins. In other words, a semiconductor fabrication process is developed.
For example, Japanese Unexamined Patent Application Publication No. Hei 9-306965 proposes a wiring evaluation circuit having a write circuit formed on an input side of an evaluation wiring and a read circuit formed on an output side of the evaluation wiring via a latch circuit. In this wiring evaluation circuit, the write circuit gives a predetermined logic level (expected value) to the evaluation wiring, the read circuit reads a logic level held by the latch circuit, and a read value is compared with the expected value, thereby detecting failure of each evaluation wiring.